It's not a layout problem. It's not a component problem. It's a mental model problem — and until you fix the vocabulary in your team's head, you'll keep losing weeks to the chamber.
Every time a hardware team walks into an EMC pre-compliance session and fails, I see the same pattern. They spent weeks adding copper tape to seams, bolting chassis panels together more aggressively, adding ferrites on every cable, and tying every ground pour to chassis at every possible point. And they still fail radiated emissions. Or they still get crushed by ESD on a front-panel port.
The root cause isn't any of those things. The root cause is the words they're using to think.
"Grounding" is the most dangerous word in hardware engineering. Not because it's wrong — it's just dangerously vague. When you tell a junior engineer to "fix the grounding," you could mean: connect to chassis, reduce impedance on a return path, eliminate a ground loop, improve the reference potential stability, or bond two structures that are floating relative to each other. These are completely different interventions. Conflating them produces random, ritualistic behaviour at the bench.
"Shielding" is the second trap. Shielding does not block fields — it redirects them, reflects them, and in the case of a good conductor, induces opposing currents that cancel incident fields. A shielding enclosure that is 98% closed and 2% open seam at the right frequency is not a shield. It's a slot antenna. Thinking of shielding as a binary ("we have a metal box, therefore we are shielded") is what produces teams that bolt a lid on a PCB and are genuinely shocked when it radiates worse than the bare board.
Every current that flows out of a source must return to that source. This is not negotiable — it is Kirchhoff's current law. The question is never whether the return current flows, it's where it flows and what area the loop it forms encloses. A large loop area is an antenna. A small loop area is a quiet circuit.
When you think "return path" instead of "ground," you immediately ask the right questions: Where does this switching current return? What impedance does that return path have at 100 MHz? Is there a discontinuity — a slot, a removed pour, a connector gap — between the signal via and the return via?
The field does not care about your ground symbol. It cares about the current loop area you have created, and it will radiate in exact proportion to that area times the current times the frequency squared.
This reframe also fixes a common DC-thinking error: teams who pour a solid ground plane and consider the problem solved. A DC ground plane and a high-frequency return path are not the same thing. A plane with a slot cut through it — even a small slot — forces return current to route around it, forming a large loop that may be orders of magnitude worse than no plane at all for that particular signal pair.
Instead of "ground," think reference plane. A reference plane has a job: it is a low-impedance, low-inductance surface that all signals within a domain can reference without their reference potential moving. A ground plane stitched to chassis at one point per board doesn't do this job at 500 MHz — the inductance of that single bond wire makes the plane's potential bounce relative to chassis at exactly the frequencies where your radiated emissions are failing.
Fields want to propagate. Your job as a designer is to define the geometry of where they are allowed to propagate and where they are not, then construct the physical structures that enforce that geometry.
Any aperture in a conductive enclosure larger than λ/20 at the frequency of concern will radiate. Ventilation holes, connector cutouts, cable entry points, seam gaps — all of them. Your emissions floor is set by your worst aperture, not your average. Divide apertures. Use wire mesh. Use conductive gaskets at seams.
A cable entering a shielded enclosure is a field guide — it carries whatever field is on the conductor straight through your containment structure. A cable filtered at the wall breaks the field propagation at the boundary. The termination geometry and bond impedance at the point of entry are everything.
Your differential pair is balanced in the schematic. It is not balanced in reality. PCB asymmetry, connector skew, and component tolerances produce a small imbalance that drives common-mode current — which radiates like a monopole antenna driven by the full cable length.
A flat copper strap looks like a short circuit at DC. At 100 MHz it is an inductor. At 500 MHz it may be a significant impedance. Your bonding strategy must be designed at the highest frequency you want to contain — multiple short, wide bonds at sub-wavelength intervals. Calculate it. Simulate it. Measure it.
Start at the design review stage. Ban the word "ground" as a verb. Make people say what they actually mean: "reduce return path inductance," "close the switching loop," "bond the chassis seam to below 10 mΩ at 200 MHz." Make people draw current return paths on the schematic and layout — not just signal paths. Make people identify every aperture and its largest linear dimension relative to λ at the clock frequency and its harmonics.
And get the whole team — firmware, mechanical, EE — into the same mental model. EMC failures are almost always system failures. The only way to align everyone is a shared, physics-based vocabulary.
Stop thinking about grounding and shielding.
Start thinking about current paths, field geometry,
and aperture control.
The test chamber is just a measurement instrument. What it's measuring is how well you understood the physics before you laid out the board. Change the model, and the results follow.
Work directly with Dario to identify return path problems, aperture risks, and common-mode failures at the design stage — before a €15,000–40,000 chamber session reveals them.