An EMI design review is not a checklist exercise. It is a structured examination of where electromagnetic fields are generated, how they propagate, and whether the design contains them. Here is how to run one.
Most EMI design reviews happen too late — after pre-compliance failure, when the board is already in hand and the schedule is already slipping. The most valuable review happens before fabrication, when every finding is a routing change rather than a respin.
An effective EMI review examines the design in a specific sequence: stackup first, then schematics, then layout. Each layer of the review builds on the previous one. Getting the sequence wrong means examining symptoms before root causes.
The stackup determines how electromagnetic fields are contained within the PCB. Before looking at a single trace or component, verify: does every signal layer have an adjacent, solid, continuous reference plane? Is the power plane separated from the signal return path? Are the high-speed layers paired with dedicated ground planes rather than power planes?
If the stackup is wrong, nothing else matters. A well-routed board on a bad stackup will still fail. Fix the stackup first.
Every signal layer must be directly adjacent to a reference (ground) plane — not separated by another signal layer or a power plane. Verify that no signal layer is "floating" without an adjacent reference. This is the single most impactful check in an EMI review.
Check that all ICs have decoupling capacitors placed directly at their power pins, that filter components are present at every I/O connector, and that switching loop areas (MOSFET — inductor — capacitor) are minimised by component proximity. These decisions are made in the schematic but have spatial consequences in the layout.
For every high-speed signal, switching node, and power rail, trace the return current path. Identify any slot, void, or gap in the reference plane that forces a detour. Flag any via transition where a return via is missing. Return path continuity is the most common source of EMC failures in otherwise competent designs.
Verify that all EMC filters are placed at the connector — at the physical edge of the board where cable interfaces exist. A filter placed 30mm from the connector with an unfiltered trace connecting them is not filtering the cable. The boundary between inside and outside must be enforced in the copper, not just the schematic.
Identify every aperture in the board that could create a discontinuity in the reference plane beneath high-speed signals. Connector footprints often create voids that split the reference plane. Mechanical cutouts may cross signal return paths. Each aperture must be assessed for impact on adjacent signal return currents.
An EMI review is not about finding problems. It is about finding them before the chamber does — when they cost a routing change rather than a respin.
In practice, most designs have a predictable set of issues when reviewed against these criteria. The stackup often has a power plane adjacent to a signal layer instead of a ground plane. Decoupling capacitors are placed near their ICs but with long via connections to the power and ground planes, creating inductive parasitic paths. Filters exist on connector interfaces but are placed 10–20mm back from the connector with unfiltered traces completing the connection. Ground plane voids exist beneath connectors or around mounting holes, creating slots in the return path for nearby signals.
None of these are exotic problems. All of them are identifiable at the design stage, before a single board is fabricated, if the review is conducted systematically with the field model in mind.
Work directly with Dario to identify EMC risks at the design stage — before a €15,000–40,000 chamber session reveals issues that require a respin.